1. Field of the Invention
The present invention relates to clock distribution in a compact peripheral component interconnect (PCI) system, and more particularly to a method and clock distribution device in a compact PCI based multi-processing system.
2. Background of the Related Art
Generally, a compact PCI based multi-processing system connects various circuit boards to its multiple slots to process multiple signals. In this structure, the system board connected to the system slot distributes the clock to the other boards so that such other boards may operate in synchronization with the supplied clock.
In a general compact PCI system, eight slots constitute a system. Among the eight slots, only one slot may function as the system slot to which the system board may be connected and the other slots function as peripheral slots to which various I/O boards may be connected.
FIG. 1 illustrates a compact PCI system of the related art. The system slot SL1, to which the system board is connected, supplies a clock to each of the peripheral slots SL2˜SL8. Thus, the system slot SL1 may supply a total of seven clocks.
Specifically, CLK0 outputted from slot 1 SL1 is connected to the clock input terminal CLK0 of slot 2 SL2. Likewise, CLK1 from SL1 is connected to the clock input terminal CLK0 of slot 3 SL3, CLK2 from SL1 to CLK0 of CL4, CLK3 from SL1 to CLK0 of SL5, CLK4 from SL1 to CLK0 of SL6, CLK5 from SL1 to CLK0 of SL7, and CLK 6 from SL1 to CLK0 of SL8. Each board connected to each slot of the peripheral slots SL2˜SL8 uses the clock supplied by SL1 internally in each board to conduct its relevant operation in synchronization with the supplied clock.
In order for the compact PCI system of the related art to efficiently operate, the clocks supplied from the system slot SL1 should not have a skew over a certain error range. Thus, to limit the error range of the skew, the compact PCI specification of the related art limits the number of slots in accordance with the used clock rate (e.g., eight slots are used for 33 MHZ clock and five slots are used for 66 MHZ clock). Furthermore, the distance between two neighboring slots is limited to be within a certain range (e.g., the distance is made not to exceed 20.32 mm).
By limiting the number of slots and the distance between slots according to the relevant clock rate, the routing length on the back-plane is maintained to be between 135 mm and 185 mm. Accordingly, the maximum skew of the clock on the back-plane does not exceed certain time. For example, if the clock is 33 MHZ, the maximum skew is 1.2 ns and if the clock is 66 MHz, the maximum skew is 0.2 ns.
In order to route the clocks CLK0˜CLK6 in compliance with the requirements of a general PCI specification, the related art general compact PCI system delays, which occur in transmitting the clocks to respective slots SL2˜SL8 from the system slot SL1, should have the same value. Accordingly, as illustrated in FIG. 1, the closer a slot is located to the system slot SL1, the greater delay is required through the relevant delay line. For example, the delay line of additional “6d” is used for slot 2 SL2 and the delay line of additional “5d” is used for slot 3 SL3. Likewise, the delay line of additional “4d” is used for slot 4 SL4, “3d” for slot 5 SL5, “2d” for slot 6 SL6, and “d” for slot 7 SL7.
Accordingly, in order to prevent the maximum skew of the clocks transmitted by the system board to the other boards from exceeding a certain limit time, the compact system of the related art delay lines are previously installed in clock transmission paths of the system. Thus, the system board may not be connected to any other board than the system slot SL1. Accordingly, flexible structuring of the system is impossible.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.